HM5112805F-6 Datasheet, PDF (16/34 Pages) Hitachi Semiconductor – 128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh

HM5112805F-6, HM5113805F-6
20. t_HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO
page mode mix cycle (1), (2)), minimum value of CAS cycle (t_CAS + t_CP + 2 t_T) becomes greater
than the specified t_HPC (min) value. The value of CAS cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between t_OHR and t_OH and between t_OFR and t_OFF.
22. t_DOH defines the time at which the output level go cross. V_OL = 0.8 V, V_OH = 2.0 V of output timing
reference level.
23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
ms period on the condition a and b below.
a. Enter self refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within
15.6µs after exiting from self refresh mode.
24. In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 23.
25 At t_RASS > 100 µs, self refresh mode is activated, and not activated at t_RASS < 10 µs. It is undefined
within the range of 10 µs ≤ t_RASS ≤ 100 µs. For t_RASS ≥ 10 µs, it is necessary to satisfy t_RPS.
26. XXX: H or L (H: V_IH (min) ≤ V_IN ≤ V_IH (max), L: V_IL (min) ≤ V_IN ≤ V_IL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied V_IH or V_IL.
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