HD74HCT137 Datasheet, PDF (1/8 Pages) Hitachi Semiconductor – 3-to-8-line Decoder/Demultiplexer with Address Latch

HD74HCT137
3-to-8-line Decoder/Demultiplexer with Address Latch
Description
The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs.
When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the
latches. As long as GL remains high no address changes will be recognized. Output enable controls, G₁
and G₂, control the state of the outputs independently of the select or latch-enable inputs.
All of the outputs are high unless G₁ is high and G₂ is low. The HD74HCT137 is ideally suited for the
implementation of glitchfree decoders in stored-address applications in bus oriented systems.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: t_pd (A, B, C to Y) = 18 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)