CD22354A Datasheet, PDF (7/10 Pages) Harris Corporation – CMOS Single-Chip, Full-Feature PCM CODEC

CD22354A, CD22357A
Electrical Specifications (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
Hold Time from 3rd Period of Bit
t_HBFI
Long Frame Sync Pulse
100
-
Clock Low to Frame Sync
(from 3 to 8-Bit Clock Periods Long)
(FS_X or FS_R)
Minimum Width of the Frame
Sync Pulse (Low Level)
t_WFL
64K Bit/s Operating Mode
160
-
NOTE:
1. For short frame sync timing, FS_X and FS_R must go high while their respective bit clocks are high.
MAX
-
UNITS
ns
-
ns
Pin Descriptions
PIN NO.
1
2
3
4
5
SYMBOL
V-
GND
VF_RO
V+
FS_R
6
D_R
7
BCLK_R/CLK-
SEL
8
MCLK_R/PDN
9
MCLK_X
10
BCLK_X
11
D_X
12
FS_X
13
TS_X
14
GS_X
15
VF_XI-
16
VF_XI+
DESCRIPTION
Negative power supply, V- = -5V ±5%.
Analog and digital ground. All signals referenced to this pin.
Analog output of RECEIVE FILTER.
Positive power supply, V+ = 5V ±5%.
Receive Frame Sync Pulse which enables BCLK_R to shift PCM data into D_R. FS_R is an 8kHz PULSE
TRAIN.
Receive Data Input. PCM data is shifted into D_R following the FS_R leading edge.
The Receive Bit Clock, which shifts data into D_R after the frame sync leading edge, may vary from 64kHz
to 2.048MHz. Alternatively, the leading edge may be a logic input which selects either 1.536MHz/
1.544MHz or 2.048MHz for Master Clock in synchronous mode and BCLK_X is used for both transmit and
receive directions.
Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLK_X,
but best performance is realized from synchronous operation. When this pin is continuously connected
low, MCLK_X is selected for all internal timing. When this pin is continuously connected high, the device is
powered down.
Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLK_R,
but best performance is realized from synchronous operation.
The Bit Clock which shifts out the PCM Data on D_X. May vary from 64kHz to 2.048MHz, but must be syn-
chronous with MCLK_X.
The THREE-STATE PCM Data Output which is enabled by FS_X.
Transmit Frame Sync Pulse input which enables BCLK_X to shift out the data on D_X. FS_X is an 8kHz
PULSE TRAIN.
Open drain output which pulses low during the encoder time slot.
Transmit gain adjust.
Inverting input of the transmit input amplifier.
Non-inverting input of the transmit input amplifier.
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