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CD22354A Datasheet, PDF (6/10 Pages) Harris Corporation – CMOS Single-Chip, Full-Feature PCM CODEC
◁
CD22354A, CD22357A
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
AC TIMING
Frequency of Master Clocks
1/tPM
Depends on the Device Used
-
and the BCLKR/CLKSEL Pin
-
MCLKX and MCLKR
-
Width of Master Clock High
tWMH
MCLKX and MCLKR
160
Width of Master Clock Low
tWML
MCLKX and MCLKR
160
Rise Time of Master Clock
tRM
MCLKX and MCLKR
-
Fall Time of Master Clock
tFM
MCLKX and MCLKR
-
Set-up Time from BCLKX High
(and FSX in Long Frame Sync
Mode) to MCLKX Falling Edge
tSBFM
First Bit Clock after the Leading
100
Edge of FSX
Period of Bit Clock
tPB
485
Width of Bit Clock High
tWBH
VIH = 2.2V
160
Width of Bit Clock Low
tWBL
VIL = 0.6V
160
Rise Time of Bit Clock
tRB
tPB = 488ns
-
Fall Time of Bit Clock
tFB
tPB = 488ns
-
Hold Time from Bit Clock Low to
tHBF
Long Frame Only
0
Frame Sync
Hold Time from Bit Clock High to
tHOLD
Short Frame Only
0
Frame Sync
Set-up Time from Frame Sync to
tSFB
Long Frame Only
80
Bit Clock Low
Delay Time from BCLKX High to
tDBD
Load = 150pF plus 2 LSTTL
0
Data Valid
Loads
Delay Time to TSX Low
tXDP
Load = 150pF plus 2 LSTTL
-
Loads
Delay Time from BCLKX Low or
tDZC
50
FSX Low to Data Output Disabled
Delay Time to Valid Data from
tDZF
CL = 0pF to 150pF
20
FSX or BCLKX, Whichever Comes
Later
Set-up Time from DR Valid to
tSDB
50
BCLKR/X Low
Hold Time from BCLKR/X Low to
tHBD
50
DR Invalid
Set-up Time from FSX/R to
BCLKX/R Low
tSF
Short Frame Sync Pulse
50
(1 or 2 Bit Clock Periods Long)
(Note 1)
Hold Time from BCLKX/R Low to
FSX/R Low
tHF
Short Frame Sync Pulse
100
(1 or 2 Bit Clock Periods Long)
(Note 1)
TYP
MAX
UNITS
1.536
-
1.544
-
2.048
-
-
-
-
-
-
50
-
50
-
-
MHz
MHz
MHz
ns
ns
ns
ns
ns
488
15,725
ns
-
-
ns
-
-
ns
-
50
ns
-
50
ns
-
-
ns
-
-
ns
-
-
ns
-
180
ns
-
140
ns
-
165
ns
-
165
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
4-170
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