CD4070B Datasheet, PDF (2/7 Pages) Texas Instruments – CMOS Quad Exclusive-OR and Exclusive-NOR Gate

Functional Diagrams
CD4070B
1
A
2
J=A⊕B ^B
K=C⊕^D _C ⁵
6
M=G⊕H ^D
L = E⊕ F
V_SS = 7
V_DD = 14
8
E
9
F
G ¹²
13
H
CD4070B, CD4077B
3
J
4
K
10
L
11 _M
CD4077B
1
A
2
B
J =A⊕B
5
K=C⊕D ^C ₆
D
M=G⊕H E ⁸
L =E⊕F F ⁹
G ¹²
13
H
3
J
4
K
10
L
11 _M
V_DD
B†
2(5, 9, 12)
A†
1(6, 8, 13)
p
nn
V_SS
p
V_DD
p
n
V_SS
V_DD
† INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
V_DD
p
p
p
J
n
3(4, 10, 11)
n
V_SS
V_DD
p
B†
p
2(5, 9, 12)
nn
n
V_SS
p
V_DD
A†
p
n
1(6, 8, 13)
n
V_SS
V_DD
† INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
V_DD
p
J
3(4, 10, 11)
n
V_SS
V_SS
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B
(1 OF 4 IDENTICAL GATES)
V_SS
FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B
(1 OF 4 IDENTICAL GATES)
CD4070B TRUTH TABLE (1 OF 4 GATES)
A
B
J
0
0
0
1
0
1
0
1
1
1
1
0
NOTE:
1 = High Level
0 = Low Level
J=A⊕B
CD4077B TRUTH TABLE (1 OF 4 GATES)
A
B
J
0
0
1
1
0
0
0
1
0
1
1
1
NOTE:
1 = High Level
0 = Low Level
J=A⊕B
2