CD4070B Datasheet, PDF (1/7 Pages) Texas Instruments – CMOS Quad Exclusive-OR and Exclusive-NOR Gate

Semiconductor
June 1998
CD4070B,
CD4077B
CMOS Quad Exclusive-OR
and Exclusive-NOR Gate
Features
Description
• High-Voltage Types (20V Rating)
• CD4070B - Quad Exclusive-OR Gate
• CD4077B - Quad Exclusive-NOR Gate
• Medium Speed Operation
- t_PHL, t_PLH = 65ns (Typ) at V_DD = 10V, C_L = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full
Package Temperature Range
- 100nA at 18V and 25^oC
• Noise Margin (Over Full Package Temperature Range)
- 1V at V_DD = 5V, 2V at V_DD = 10V, 2.5V at V_DD = 15V
• Meets All Requirements of JEDEC Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series
CMOS Devices
The Harris CD4070B contains four independent Exclusive-
OR gates. The Harris CD4077B contains four independent
Exclusive-NOR gates.
The CD4070B and CD4077B provide the system designer
with a means for direct implementation of the Exclusive-OR
and Exclusive-NOR functions, respectively.
Ordering Information
TEMP.
PART NUMBER RANGE (^oC)
PACKAGE
CD4070BE
-55 to 125 14 Ld PDIP
CD4077BE
-55 to 125 14 Ld PDIP
CD4070BF
-55 to 125 14 Ld CERDIP
CD4077BF
-55 to 125 14 Ld CERDIP
CD4070BM
-55 to 125 14 Ld SOIC
PKG.
NO.
E14.3
E14.3
F14.3
F14.3
M14.15
Applications
CD4077BM
-55 to 125 14 Ld SOIC
M14.15
• Logical Comparators
• Adders/Subtractors
• Parity Generators and Checkers
Pinouts
CD4070B
(PDIP, CERDIP, SOIC)
TOP VIEW
CD4077B
(PDIP, CERDIP, SOIC)
TOP VIEW
A1
B2
J=A⊕B 3
K=C⊕D 4
C5
D6
V_SS 7
14 V_DD
13 H
12 G
11 M = G ⊕ H
10 L = E ⊕ F
9F
8E
A1
B2
J=A⊕B 3
K=C⊕D 4
C5
D6
V_SS 7
14 V_DD
13 H
12 G
11 M = G ⊕ H
10 L = E ⊕ F
9F
8E
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
1
File Number 910.1