CD22402 Datasheet, PDF (1/11 Pages) Harris Corporation – Sync Generator for TV Applications and Video Processing Systems

May 1999
CD22402 ^{Semiconductor}
NO
Call
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[ /Title
(CD2240
2)
/Subject
(Sync
Genera-
tor for
TV
Applica-
tions and
Video
Process-
Features
• Interlaced Composite Sync Output
• Automatic Genlock Capability
• Crystal Oscillator Operation
• 525 or 625 Line Operation
• Vertical Reset Option
• Wide Power Supply Operating Voltage . . . . . 4V to 15V
Applications
• Cameras
• Monitors and Displays
• CATV
• Teletext
• Video Games
• Sync Restorer
• Video Service Instruments
Part Number Information
PART NUMBER
CD22402D
CD22402E
TEMP.
RANGE (^oC)
PACKAGE
-55 to 125 24 Ld SBDIP
-40 to 85 24 Ld PDIP
PKG.
NO.
D24.6
E24.6
Description
The Harris CD22402 (Note) is a CMOS LSI sync generator that
produces all the timing signals required to drive a fully 2-to-1
interlaced 525-line 30-frame/second, or 625-line 25-frame/sec-
ond TV camera or video processing system. A complete sync
waveform is produced which begins each field with six serrated
vertical sync pulses, preceded and followed by six half-width
double frequency equalizing pulses. The sync output is gated by
the master clock to preserve horizontal phase continuity during
the vertical interval.
The CD22402 can be operated either in “genlock” mode, in
which it is synchronized with a reference sync pulse train from
another TV camera, or in “stand-alone” mode, in which it is syn-
chronized with a local on-chip crystal oscillator (the crystal and
two passive components are off chip). Also, the circuit can
sense the presence or absence of a reference sync pulse train
and automatically select the “genlock” or “stand-alone” mode.
A frame sync pulse is produced at the beginning of every odd
field. The vertical counter can be reset to either the first equalizing
pulse or the first vertical sync pulse of the vertical interval. The
interlaced sync provided by the CD22402 differs from RS-170 by
having slightly narrower sync and equalizing pulses. The clock
frequency of 32 times horizontal rate allows for approximately 4µs
horizontal pulse widths and 2µs equalizing pulses. Otherwise
operation can be phase locked to a color sub-carrier for a full
interlaced operating system.
The CD22402 is operable with a single supply over a voltage
range of 4V to 15V.
Pinout
CD22402 (PDIP, SBDIP)
TOP VIEW
DELAY, GENLOCK TO CRYSTAL OSCILLATOR 1
CRYSTAL OSCILLATOR FEEDBACK TAP 2
V_SS 3
HORIZONTAL DRIVE OUTPUT 4
MIXED SYNC OUTPUT ⁵
GENLOCK OSCILLATOR CAPACITOR CONNECTION 6
MIXED BEAM BLANKING OUTPUT 7
VERTICAL COUNTER RESET TO FIRST EQUALIZING PULSE 8
VERTICAL DRIVE OUTPUT 9
VERTICAL RESET TO FIRST VERTICAL SYNC PULSE ¹⁰
HORIZONTAL CLAMP OUTPUT ¹¹
V_SS 12
24 RESISTOR CONNECTION FOR GENLOCK OSCILLATOR
23 MASTER FREQUENCY INPUT
22 R-C CONNECTION FOR GENLOCK OSCILLATOR
21 DELAY, GENLOCK TO CRYSTAL OSCILLATOR
20 GENLOCK INPUT (COMPOSITE SYNC)
19 _VDD
18 525 LINE TO 625 LINE OPERATION SWITCH
17 VERTICAL PROCESSING BLANKING OUTPUT
16 SHORT VERTICAL DRIVE OUTPUT
15 FRAME SYNC OUTPUT (ODD FIELD)
14 HORIZONTAL PROCESSING BLANKING OUTPUT
13 MIXED PROCESSING BLANKING OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1999
8-40
File Number 1686.5