HSD8M64B4W Datasheet, PDF (9/10 Pages) Hanbit Electronics Co.,Ltd – Synchronous DRAM Module 64Mbyte(8Mx64-Bit), 144pin SO-DIMM, 4Banks, 4K Ref., 3.3V

HANBit
HSD8M64B4W
SIMPLIFIED TRUTH TABLE
COMMAND
CKE
n-1
CK
E
n
/C
S
/R
A
S
/C
A
S
/W
E
D
Q
M
BA A10/
0,1 AP
A11
A9~A0
NOT
E
Register Mode register set
H
X
L
L
L
L
X
OP code
1,2
Auto refresh
H
3
H
L
L
L
HX
X
Self Entry
L
3
Refresh
refres
LHHH
3
Exit
L
H
X
X
h
HXX X
3
Bank active & row addr.
H
X
L
L
H
H XV
Row address
Auto
precharge
Read &
disable
column
H
Auto
precharge
address
disable
Column
L
4
Address
X L H L H XV
(A0 ~
H
4,5
A8)
Column
Auto
precharge
Write &
disable
column
H
address
Auto
precharge
disable
XLHL
L XV
Address
L
4
(A0 ~
A8)
H
4,5
Burst Stop
H
X
L
L
H
L
X
X
6
Precharg Bank selection
e
All banks
V
L
H
X
L
L
H
L
X
X
X
H
HXX X
Clock suspend or Entry
H
L
X
LVVV
X
active power down
Exit
L
HXXX XX
HXX X
Entry
H
L
X
Precharge power
LHHH
X
down mode
HXX X
Exit
L
H
X
LVVV
DQM
H
X
V
X
7
HXXX
No operation command
H
X
X
X
L HHH
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
URL:www.hbe.co.kr
REV.1.0 (August.2002)
9
HANBit Electronics Co.,Ltd.