HSD8M64D8H Datasheet, PDF (7/10 Pages) Hanbit Electronics Co.,Ltd – Synchronous DRAM Module 64Mbyte (8Mx64bit), DIMM based on 8Mx8,4Banks, 4K Ref., 3.3V

HANBit
HSD8M64D8H
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
PARAMETER
SYMBOL
VERSION
-13
-10
-10L
UNIT NOTE
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
t_RRD(min)
15
20
20
ns
1
t_RP(min)
20
20
20
ns
1
t_RP(min)
20
20
20
ns
1
t_RAS(min)
45
50
50
ns
1
t_RAS(max)
100
ns
Row cycle time
tRC^(min)
Last data in to row precharge
t_RDL(min)
Last data in to Active delay
t_DAL(min)
Last data in to new col. address delay
t_CDL(min)
Last data in to burst stop
t_BDL(min)
Col. address to col. address delay
t_CCD(min)
CAS latency=3
Number of valid output data
CAS latency=2
65
-
70
2
2 CLK + 20 ns
1
1
1
2
70
1
ns
1
CLK
2
-
CLK
2
CLK
2
CLK
3
ea
4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
.5. For -8/H/L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
PARAMETER
SYMBOL
-13
MIN MAX
CLK cycle time
CAS
latency=3
CAS
latency=2
7.5
t_CC
1000
-
CLK to valid
CAS
output delay
latency=3
CAS
t_SAC
latency=2
5.4
-
Output data
hold time
CAS
latency=3
CAS
latency=2
2.7
t_OH
-
CLK high pulse width
t_CH
2.5
-10
MIN MAX
10
1000
10
6
6
3
3
3
-10L
MIN MAX
10
1000
12
6
7
3
3
3
CLK low pulse width
t_CL
2.5
3
3
Input setup time
t_SS
1.5
2
2
Input hold time
t_SH
0.8
1
1
CLK to output in Low-Z
t_SLZ
1
1
1
CLK to output CAS
in Hi-Z
latency=3
CAS
t_SHZ
latency=2
5.4
6
6
-
6
7
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered
ie., [(tr + tf)/2-1]ns should be added to the parameter.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE
1
1,2
2
3
3
3
3
3
2
URL:www.hbe.co.kr
REV.1.0(August.2002)
7
HANBit Electronics Co.,Ltd.