HSD64M72D18RP Datasheet, PDF (7/11 Pages) Hanbit Electronics Co.,Ltd – Synchronous DRAM Module 512Mbyte (64Mx72bit), DIMM with PLL & Register based on 64Mx4, 4Banks, 8K Ref., 3.3V

HANBit
AC OPERATING TEST CONDITIONS
(vcc = 3.3V ± 0.3V, T_A = 0 to 70°C)
PARAMETER
AC Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
+3.3V
HSD64M72D18RP
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
UNIT
V
V
ns
V
D_OUT 870Ω
1200Ω
50pF*
V_OH (DC) = 2.4V, I_OH = -2mA ^DOUT
V_OL (DC) = 0.4V, I_OL = 2mA
(Fig. 1) DC output load
vss
V_tt=1.4V
Z0=50Ω
50Ω
50pF
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
PARAMETER
SYMBOL
Row active to row active delay
/RAS to /CAS delay
Row precharge time
Row active time
t_RRD(min)
t_RCD(min)
t_RP(min)
t_RAS(min)
t_RAS(max)
Row cycle time
t_RC(min)
Last data in to row precharge
t_RDL(min)
Last data in to Active delay
t_DAL(min)
Last data in to new col. address delay
t_CDL(min)
Last data in to burst stop
t_BDL(min)
Col. address to col. address delay
t_CCD(min)
Number of valid output data
CAS latency=3
-
URL:www.hbe.co.kr
7
REV.1.0 (August.2002)
VERSION
-13
-10
-10L
15
20
20
20
20
20
20
20
20
45
50
50
UNIT NOTE
ns
1
ns
1
ns
1
ns
1
100
ns
65
70
70
2
2CLK + 20ns
1
1
1
2
-
1
ns
1
CLK
2,5
-
5
CLK
2
CLK
2
CLK
3
ea
4
HANBit Electronics Co.,Ltd.