HMS12864F8VL Datasheet, PDF (7/9 Pages) Hanbit Electronics Co.,Ltd – SRAM MODULE 1MByte (128K x 64 bit), 120-Pin SMM, 3.3V

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TIMING WAVEFORM OF WRITE CYCLE ( /OE Low Fixed )
HMS12864F8VL
Address
/CE
/WE
Data In
Data Out
t_AS(4)
High-Z
t_WHZ(6,7)
t_AW
t_CW(3)
t_WR(5)
t_OH
t_WP(2)
t_DW
t_DH
Data Valid
t_OW
High-
(10)
(9)
Notes(Write Cycle)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among
/CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high.
t_WP is measured from the beginning of write to the end of write.
3. t_CW is measured from the later of /CE going low to the end of write.
4. t_AS is measured from the address valid to the beginning of write.
5. t_WR is measured from the end of write to the address change. t_WR applied in case a write ends as /CE, or /WE going high.
6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite
phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state.
9. D_OUT is the read data of the new address.
10. When /CE is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output
should not be applied.
FUNCTIONAL DESCRIPTION
/CE
/WE
/OE
H
X*
X
L
H
H
L
H
L
L
L
X
Note: X means Don't Care
MODE
Not Select
Output Disable
Read
Write
I/O PIN
High-Z
High-Z
D_OUT
D_IN
SUPPLY CURRENT
l _SB, l _SB1
l_CC
l_CC
l_CC
7
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