HMS12864F8VL Datasheet, PDF (6/9 Pages) Hanbit Electronics Co.,Ltd – SRAM MODULE 1MByte (128K x 64 bit), 120-Pin SMM, 3.3V

HANBit
HMS12864F8VL
TIMING WAVEFORM OF READ CYCLE ( /CE Controlled )
t_RC
Address
/CE
/OE
t_AA
t_CO
t_LZ(4,5)
t_OE
t_OLZ
Data Out
High-Z
Vcc Supply
l_CC
Current
l_SB
t_PU
50%
t_HZ(3,4,5)
t_OHZ
t_OH
t_PD
50%
Notes (Read Cycle)
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to first transition address.
3. t_HZ and t_OHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V_OH
or V_OL levels.
4. At any given temperature and voltage condition, t_HZ (max.) is less than t_LZ (min.) both for a given device and from device
to device.
5. Transition is measured ± 200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with /CE = V_IL.
7. Address valid prior to coincident with /CE transition low.
TIMING WAVEFORM OF WRITE CYCLE (/OE=Clock )
Address
/OE
/CE
/WE
Data In
Data Out
t_WC
t_AW
t_WR(5)
t_AS(4)
t_CW(3)
t_WP(2)
High-Z
t_OHZ(6)
6
t_DW
t_DH
Data Valid
t_OW
High-Z
HANBit Electronics Co.,Ltd.