HSD64M64F8KA Datasheet, PDF (6/10 Pages) Hanbit Electronics Co.,Ltd – Synchronous DRAM Module 512Mbyte (64Mx64bit), SMM, based on 32Mx8 ,4Banks, 4K Ref., 3.3V

HANBit
HSD64M64F8KA
+3.3V
D_OUT
870Ω
1200Ω
50pF*
D_OUT
V_OH (DC) = 2.4V, I_OH = -2mA
vss VOL (DC) = 0.4V, IOL = 2mA
(Fig. 1) DC output load
V_tt=1.4V
Z0=50Ω
50Ω
50pF
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
PARAMETER
SYMBOL
Row active to row active delay
/RAS to /CAS delay
Row precharge time
Row active time
t_RRD(min)
t_RCD(min)
t_RP(min)
t_RAS(min)
t_RAS(max)
Row cycle time
t_RC(min)
Last data in to row precharge
t_RDL(min)
Last data in to Active delay
t_DAL(min)
Last data in to new col. address delay
t_CDL(min)
Last data in to burst stop
t_BDL(min)
Col. address to col. address delay
t_CCD(min)
Number of valid output data
CAS latency=3
CAS latency=2
VERSION
-10
-10L
-13
20
20
15
20
20
20
20
20
20
50
50
45
100
70
70
65
2
2 CLK + 20 ns
1
1
1
2
1
UNIT NOTE
ns
1
ns
1
ns
1
ns
1
ns
ns
1
CLK
2,5
-
5
CLK
2
CLK
2
CLK
3
ea
4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)
URL:www.hbe.co.kr
REV. 1.0 (August, 2002)
6
HANBit Electronics Co.,Ltd.