HMS1M32M8S Datasheet, PDF (6/10 Pages) Hanbit Electronics Co.,Ltd – High-Speed SRAM MODULE 4Mbyte(1M x 32-Bit)

HANBit
HMS1M32M8S
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE (Address Controlled) ( /CE = /OE = V_IL , /WE = V_IH)
Address
Data out
Previous Data Valid
t_RC
t_AA
t_OH
Data Valid
TIMING WAVEFORM OF READ CYCLE (/WE = V_IH )
t_RC
Address
/CE
/OE
t_AA
t_CO
t_LZ(4)
t_OE
t_OLZ
Data Out
High-Z
Data Valid
t_HZ(3,4)
t_OHZ
t_OH
Notes (Read Cycle)
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to first transition address.
3. t_HZ and t_OHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V_OH
or V_OL levels.
4. At any given temperature and voltage condition, t_HZ (max.) is less than t_LZ (min.) both for a given device and from device
to device.
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