HMN2M8D Datasheet, PDF (6/9 Pages) Hanbit Electronics Co.,Ltd – Non-Volatile SRAM MODULE 16Mbit (2,048K x 8-Bit), 36Pin-DIP, 5V

HANBit
HMN2M8D
POWER-DOWN/POWER-UP CYCLE (T_A= T_OPR, V_CC=5V)
PARAMETER
SYMBOL
CONDITIONS
MIN
V_CC slew, 4.75 to 4.25V
t_PF
300
V_CC slew, 4.75 to V_SO
t_FS
10
V_CC slew, V_SO to V_PFD (max)
t_PU
0
Chip enable recovery time
Time during which SRAM
t_CER
is write-protected after V_CC
passes V_PFD on power-up.
40
Data-retention time in
Absence of V_CC
t_DR
T_A = 25℃
5
Write-protect time
Delay after Vcc slews down
t_WPT
past V_PFD before SRAM is
Write-protected.
40
TYP.
-
-
-
MAX
-
-
-
UNIT
㎲
㎲
㎲
80
120
ms
-
-
years
100
150
㎲
TIMING WAVEFORM
- Read Cycle No.1 (Address Access)*^1,2
Address
DOUT
tRC
tACC
tOH
Previous Data Valid
- Read Cycle No.2 (/CE Access)^*1,3,4
tRC
/CE
DOUT
tACE
tCLZ
High-Z
Data Valid
tCHZ
High-Z
URL : www.hbe.co.kr
Rev. 1.0 (May, 2002)
6
HANBit Electronics Co.,Ltd