English
Language : 

HMN2M8D Datasheet, PDF (5/9 Pages) Hanbit Electronics Co.,Ltd – Non-Volatile SRAM MODULE 16Mbit (2,048K x 8-Bit), 36Pin-DIP, 5V
◁
HANBit
HMN2M8D
READ CYCLE (TA= TOPR, VCCmin £ VCC≤ VCCmax )
PARAMETER
SYMBOL CONDITIONS
-70
-85
-120
-150
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
Read Cycle Time
tRC
70
-
85
- 120 - 150 -
ns
Address Access Time
tACC
Output load A
-
70
-
85
- 120 - 150 ns
Chip enable access time
tACE
Output load A
-
70
-
85
- 120 - 150 ns
Output enable to Output valid
tOE
Output load A
-
35
-
45
-
60
-
70
ns
Chip enable to output in low Z
tCLZ
Output load B 5
-
5
-
5
-
10
-
ns
Output enable to output in low Z
tOLZ
Output load B 5
-
0
-
0
-
5
-
ns
Chip disable to output in high Z
tCHZ
Output load B 0 25 0 35 0 45 0 60 ns
Output disable to output high Z
tOHZ
Output load B 0 25 0 25 0 35 0 50 ns
Output hold from address change
tOH
Output load A 10
-
10
-
10
-
10
-
ns
WRITE CYCLE (TA= TOPR, Vccmin £ Vcc ≤ Vccmax )
PARAMETER
-70
-85
-120
-150
UNI
SYMBOL CONDITIONS
MIN MAX MIN MAX MIN MAX Min Max T
Write Cycle Time
tWC
70
-
85
- 120 - 150 -
ns
Chip enable to end of write
tCW
Note 1
65
-
75
- 100 - 100 -
ns
Address setup time
tAS
Note 2
0
-
0
-
0
-
0
-
ns
Address valid to end of write
tAW
Note 1
65
-
75
- 100 -
90
-
ns
Write pulse width
tWP
Note 1
55
-
65
-
85
-
90
-
ns
Write recovery time (write cycle 1)
tWR1
Note 3
5
-
5
-
5
-
5
-
ns
Write recovery time (write cycle 2)
tWR2
Note 3
15
-
15
-
15
-
15
-
ns
Data valid to end of write
tDW
30
-
35
-
45
-
50
-
ns
Data hold time (write cycle 1)
tDH1
Note 4
0
-
0
-
0
-
0
-
ns
Data hold time (write cycle 2)
tDH2
Note 4
10
-
10
-
10
-
0
-
ns
Write enabled to output in high Z
tWZ
Note 5
0
25
0
30
0
40
0
50 ns
Output active from end of write
tOW
Note 5
5
-
0
-
0
-
5
-
ns
NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high.
2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE
going low and /WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high-
impedance state.
URL : www.hbe.co.kr
Rev. 1.0 (May, 2002)
5
HANBit Electronics Co.,Ltd
 ▷