S11071-1004_15 Datasheet, PDF (2/10 Pages) Hamamatsu Corporation – CCD image sensors

CCD image sensors
S11071/S10420-01 series
Structure
Parameter
S11071 series
S10420-01 series
Pixel size (H × V)
14 × 14 μm
Vertical clock phase
2-phase
Horizontal clock phase
4-phase
Output circuit
Two-stage MOSFET source follower
One-stage MOSFET source follower
Package
Window material*¹
24-pin ceramic DIP (refer to dimensional outline)
Quartz glass*²
Cooling
Non-cooled
*1: Temporary window type (ex: S11071-1106N, S10420-1106N-01) is available upon request.
*2: Resin sealing
Absolute maximum ratings (Ta=25 °C)
Parameter
Operating temperature*³
Symbol
Min.
Typ.
Max.
Unit
Topr
-50
-
+50
°C
Storage temperature
Tstg
-50
-
+70
°C
Output transistor
drain voltage
S11071 series
S10420-01 series
VOD
-0.5
-0.5
-
-
+25
+30
V
Reset drain voltage
VRD
-0.5
-
+18
V
Output amplifier return voltage
Vret
-0.5
-
+18
V
Overflow drain voltage
VOFD
-0.5
-
+18
V
Vertical input source voltage
VISV
-0.5
-
+18
V
Horizontal input source voltage
VISH
-0.5
-
+18
V
Overflow gate voltage
VOFG
-10
-
+15
V
Vertical input gate voltage
VIG1V, VIG2V
-10
-
+15
V
Horizontal input gate voltage
VIG1H, VIG2H
-10
-
+15
V
Summing gate voltage
VSG
-10
-
+15
V
Output gate voltage
VOG
-10
-
+15
V
Reset gate voltage
VRG
-10
-
+15
V
Transfer gate voltage
VTG
-10
-
+15
V
Vertical shift register clock voltage
VP1V, VP2V
-10
-
+15
V
Horizontal shift register clock voltage
VP1H, VP2H
VP3H, VP4H
-10
-
+15
V
*3: Package temperature
Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the
product within the absolute maximum ratings.
Operating conditions (MPP mode, Ta=25 °C)
Parameter
Symbol
S11071 series
S10420-01 series
Min. Typ. Max. Min. Typ. Max.
Unit
Output transistor drain voltage
VOD
12
15
18
23
24
25
V
Reset drain voltage
VRD
14
15
16
11
12
13
V
Overflow drain voltage
VOFD
11
12
13
11
12
13
V
Overflow gate voltage
VOFG
0
13
14
0
12
13
V
Output gate voltage
VOG
4
5
6
4
5
6
V
Substrate voltage
Output amplifier return voltage*⁴
VSS
-
0
-
-
0
-
V
Vret
-
1
2
V
Input source
VISV, VISH
-
VRD
-
-
VRD
-
V
Test point
Vertical input gate
VIG1V, VIG2V -9
-8
-
-9
-8
-
V
Horizontal input gate
VIG1H, VIG2H -9
-8
-
-9
-8
-
V
High VP1VH, VP2VH 4
6
8
4
6
8
Vertical shift register clock voltage
Low
VP1VL, VP2VL -9
-8
-7
-9
-8
-7
V
Horizontal shift register clock voltage
High
Low
VP1HH, VP2HH
VP3HH, VP4HH
4
VP1HL, VP2HL
VP3HL, VP4HL
-6
6
-5
8
-4
4
-6
6
-5
8
-4
V
Summing gate voltage
High
Low
VSGH
VSGL
4
6
8
4
6
8
-6
-5
-4
-6
-5
-4
V
Reset gate voltage
High
Low
VRGH
VRGL
4
6
8
4
6
8
-6
-5
-4
-6
-5
-4
V
Transfer gate voltage
High
Low
VTGH
VTGL
4
6
8
4
6
8
-9
-8
-7
-9
-8
-7
V
External load resistance
RL
2.0
2.2
2.4
90
100 110
kΩ
*4: Output amplifier return voltage is a positive voltage with respect to Substrate voltage, but the current flows in the direction of flow
out of the sensor.
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