GS82582S18 Datasheet, PDF (9/31 Pages) GSI Technology – 288Mb SigmaSIOTM DDR-II Burst of 2 SRAM

GS82582S18/36GE-400/375/333/300/250
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaSIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected
to V_SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching
with a vendor-specified tolerance is between 175 and 350. Periodic readjustment of the output driver impedance is necessary as
the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for
drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts
again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The
output driver is implemented with discrete binary weighted impedance steps.
Power-Up Initialization
After power-up, stable input clocks must be applied to the device for 20 s prior to issuing read and write commands. See the t_KInit
timing parameter in the AC Electrical Characteristics section.
Note:
The t_KInit requirement is independent of the tLock requirement, which specifies how many cycles of stable input clocks (2048)
must be applied after the Doff pin has been driven High in order to ensure that the DLL locks properly (and the DLL must lock
properly before issuing read and write commands). However, t_KInit is greater than t_KLock, even at the slowest permitted cycle time
of 8.4 ns (2048*8.4 ns = 17.2 s). Consequently, the 20 s associated with t_KInit is sufficient to cover the t_KLock requirement at
power-up if the Doff pin is driven High prior to the start of the 20 s period.
Also, t_KInit only needs to be met once, immediately after power-up, whereas t_KLock must be met any time the DLL is disabled/reset
(whether by toggling Doff Low or by stopping K clocks for > 30 ns).
Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table
A
LD
R/W
Current
Operation
D
D
K
K
K
K
(t_n)
(t_n)
(t_n)
(t_n)
K
(t_{n + 1})
K
(t_{n + 1½})
X
1
X
Deselect
X
X
V
0
1
Read
X
X
V
0
0
Write
D0
D1
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.
3. D0 and D1 indicate the first and second pieces of input data transferred during Write operations.
4. Users should not clock in metastable addresses.
Q
K
(t_{n + 1½})
Hi-Z
Q0
Hi-Z
Q
K
(t_{n + 2})
Hi-Z
Q1
Hi-Z
Rev: 1.04 4/2016
9/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology