GS82032 Datasheet, PDF (8/23 Pages) GSI Technology – 64K x 32 2M Synchronous Burst SRAM

GS82032AT/Q-180/166/133/100
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
First Write ^R
CW
CR
W
First Read ^X
CW
CR
W
X
R
Burst Write
CR
CW
R
W
Burst Read ^X
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions, plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G high) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in gray assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data
Input Set Up Time.
Rev: 1.09 7/2002
8/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.