GS82032 Datasheet, PDF (15/23 Pages) GSI Technology – 64K x 32 2M Synchronous Burst SRAM

Flow Through Read Cycle Timing
GS82032AT/Q-180/166/133/100
CK
ADSP
ADSC
ADV
A0–An
GW
BW
Single Read
tS tH
tKH
Burst Read
tKL
tKC ^{ADSP is blocked by E1 inactive}
tS tH
ADSC initiated read
tS tH
Suspend Burst
Suspend Burst
tS tH
RD1
tS
RD2
RD3
tH
tS
tH
BA–BD
E1
E2
E3
G
DQA–DQD
tS tH
E1 masks ADSP
tS tH
tS _tH
E2 and E3 only sampled with ADSP or ADSC
tOE ^tOHZ
tOLZ
Q1A
Hi-Z
tLZ
tKQ
tKQX
Q2A
Q2B
Q2C
Q2D
Deselected with E2
tKQX
Q3A
tHZ
Rev: 1.09 7/2002
15/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.