GS816036DGT-150I Datasheet, PDF (7/25 Pages) GSI Technology – 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

GS816018/32/36DGT-400/375/333/250/200/150
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
L
LBO
H
Linear Burst
Interleaved Burst
Output Register Control
L
FT
H or NC
Flow Through
Pipeline
Power Down Control
L or NC
ZZ
H
Active
Standby, I_DD = I_SB
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0]
1st address
00
01
10
2nd address
01
10
11
3rd address
10
11
00
4th address
11
00
01
Note:
The burst counter wraps to initial state on the 5th clock.
A[1:0]
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0]
1st address
00
01
10
2nd address
01
00
11
3rd address
10
11
00
4th address
11
10
01
Note:
The burst counter wraps to initial state on the 5th clock.
A[1:0]
11
10
01
00
Rev: 1.03a 9/2013
7/24
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology