GS81313LD36GK-714I Datasheet, PDF (6/26 Pages) GSI Technology – 4Mb x 36 and 8Mb x 18 organizations available

GS81313LD18/36GK-833/714/625
Power-Up and Reset Requirements
For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
V_SS, V_DD, V_DDQ, V_REF and inputs.
Power supplies must power down simultaneously, or in the reverse sequence.
After power supplies power up, the following start-up sequence must be followed.
Step 1 (Recommended, but not required): Assert RST High for at least 1ms.
While RST is asserted high:
• The PLL is disabled.
• The states of R, and W control inputs are ignored.
Note: If possible, RST should be asserted High before input clocks begin toggling, and remain asserted High until input clocks are
stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing trouble in the SRAM.
Step 2: Begin toggling input clocks.
After input clocks begin toggling, but not necessarily within specification:
• Q are placed in the non-Read state, and remain so until the first Read operation.
• QVLD are driven Low, and remain so until the first Read operation.
• CQ, CQ begin toggling, but not necessarily within specification.
Step 3: Wait until input clocks are stable and toggling within specification.
Step 4: De-assert RST Low (if asserted High).
Step 5: Wait at least 224K (229,376) cycles.
During this time:
• Driver and ODT impedances are calibrated. Can take up to 160K cycles.
• The current source for the PLL is calibrated (based on RCS pin). Can take up to 64K cycles.
Note: The PLL pin may be asserted High or de-asserted Low during this time. If asserted High, PLL synchronization begins
immediately after the current source for the PLL is calibrated. If de-asserted Low, PLL synchronization begins after the PLL pin is
asserted High (see Step 6). In either case, Step 7 must follow thereafter.
Step 6: Assert PLL pin High (if de-asserted Low).
Step 7: Wait at least 64K (65,536) cycles for the PLL to lock.
After the PLL has locked:
• CQ, CQ begin toggling within specification.
Step 8: Begin initiating Read and Write operations.
Reset Usage
Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence
described above, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently de-asserted
Low (as in Step 4 above), Steps 5~7 above must be followed before Read and Write operations are initiated.
Note: Memory array content may be perturbed/corrupted when RST is asserted High.
Rev: 1.13 7/2016
6/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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