GS8320E18T-V Datasheet, PDF(5/24 Page) GSI Technology – 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

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GS8320E18T-V Datasheet, PDF (5/24 Pages) GSI Technology – 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

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TQFP Pin Description

Symbol

A0, A1

A

DQA

DQB1

DQC

DQD

NC

BW

BA, BB

BC, BD

CK

GW

E1, E3

E2

G

ADV

ADSP, ADSC

ZZ

FT

LBO

VDD

VSS

VDDQ

Type

I

I

I/O

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

Preliminary

GS8320E18/32/36T-xxxV

Description

Address field LSBs and Address Counter preset Inputs

Address Inputs

Data Input and Output pins

No Connect

Byte WriteâWrites all enabled bytes; active low

Byte Write Enable for DQA, DQB Data I/Os; active low

Byte Write Enable for DQC, DQD Data I/Os; active low

Clock Input Signal; active high

Global Write EnableâWrites all bytes; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Core power supply

I/O and Core Ground

Output driver power supply

Rev: 1.03 6/2006

5/24

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Â© 2001, GSI Technology

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