GS8320E18T-V Datasheet, PDF (11/24 Pages) GSI Technology – 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

Simplified State Diagram with G
Preliminary
GS8320E18/32/36T-xxxV
X
Deselect
W
R
W
R
X
First Write ^R
CW
CR
W
First Read ^X
CW
CR
W
X
R
Burst Write
CR
CW
R
W
Burst Read ^X
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.03 6/2006
11/24
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology