GS8160F18T Datasheet, PDF (5/22 Pages) GSI Technology – 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

TQFP Pin Description
Symbol
A0, A1
A
DQA
DQB
DQC
DQD
NC
BW
BA, BB, BC, BD
CK
GW
E1, E3
E2
G
ADV
ADSP, ADSC
ZZ
LBO
V_DD
V_SS
V_DDQ
Type
I
I
I/O
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
GS8160F18/32/36T-5.5/6/6.5/7/7.5/8.5
Description
Address field LSBs and Address Counter preset Inputs
Address Input
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 2.12 11/2004
5/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology