GS81314LQ18GK-133 Datasheet, PDF (40/40 Pages) GSI Technology – Burst of 2 Multi-Bank ECCRAM

Revision History
Rev. Code
GS81314LQ1836GK_r1
GS81314LQ1836GK_r1.01
GS81314LQ1836GK_r1.02
GS81314LQ1836GK_r1.03
GS81314LQ1836GK_r1.04
GS81314LQ1836GK_r1.05
GS81314LQ1836GK_r1.06
GS81314LQ1836GK_r1.07
GS81314LQ1836GK_r1.08
GS81314LQ1836GK_r1.09
GS81314LQ18/36GK-133/120/106
Types of Changes
Format or Content
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Content
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Revisions
• Creation of new datasheet
• Changed Loopback Latency to 7 cycles, regardless of Read Latency.
• Removed leaded BGA package support.
• Removed 4th digit from all speed bins.
• Redefined Bank Address pins.
• Increased V_DD (max) to 1.35V.
• Added package thermal impedances.
• Redefined OFR[2:0] bits in Configuration Reg #1 as RSVD[2:0].
• Revised t_KHKDH specs.
• Revised t_KHQV, t_KHQX, and t_KHCQH specs.
• Revised t_CQHQV and t_CQHQX specs.
• Revised t_IPW specs.
• Banner changed to “Preliminary”, to reflect ES status.
• Add I_DD specifications.
• Changed -125 speed bin to -120. Changed -110 speed bin to -106.
Removed -100 speed bin.
• Removed RL=5 support (created new RL=5 -specific datasheet with
no bank restrictions; see GS81314LQ1937GK).
• Removed R(n) <> R(n-1) bank restrictions from all but -133 devices.
• Reduced V_DD (min) requirement for -120 speed bin to 1.15V, to allow
for 1.2V nominal V_DD.
• Removed “Preliminary” from data sheets.
• Increased V_DD (min) to 1.2V for 1066 MHz and 1200 MHz speed
bins. V_DD (min) is now the same value for all speed bins.
Rev: 1.09 5/2016
40/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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