GS81314LQ18GK-133 Datasheet, PDF (20/40 Pages) GSI Technology – Burst of 2 Multi-Bank ECCRAM

GS81314LQ18/36GK-133/120/106
Read Latency
Read Latency (i.e. the number of cycles from read command input to first read data output) is specified as follows:
Read Latency
6 cycles
Comment
First read data output 6 cycles after read command input
Note: The RLM register bit must remain “1” in these devices while initiating Read operations, to keep Read Latency = 6 cycles.
Write Latency
Write Latency (i.e. the number of cycles from write command input to first write data input) is specified as follows:
Write Latency
0 cycles
Comment
First write data input concurrent with write command input
Read / Write Coherency
These devices are fully coherent. That is, Read operations always return the most recently written data to a particular address, even
when a Read operation to a particular address occurs one cycle after a Write operation to the same address.
If a Read and Write operation are initiated to the same address in the same cycle, the Read operation returns the previous write data
associated with a previous Write operation (which may have occurred as little as one cycle earlier), not the current write data asso-
ciated with the current Write operation.
Rev: 1.09 5/2016
20/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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