GS8162V72CC Datasheet, PDF (4/29 Pages) GSI Technology – 256K x 72 18Mb S/DCD Sync Burst SRAMs

Preliminary
GS8162V72CC-333/300/250/200/150
GS8162V72C Block Diagram
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
Register
DQ
A0
A1
A0
D0
Q0 _A1
D1
Q1
Counter
Load
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
E1
DQ
E3
E2
Register
DQ
FT
G
Power Down
ZZ
Control
Note: Only x36 version shown for simplicity.
SCD
A
Memory
Array
Q
36
D
36
4
36
36
36
36
DQx1–DQx9
Rev: 1.01 2/2005
4/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology