GS8162V72CC Datasheet, PDF (26/29 Pages) GSI Technology – 256K x 72 18Mb S/DCD Sync Burst SRAMs

TCK
TDI
TMS
TDO
Parallel SRAM input
Preliminary
GS8162V72CC-333/300/250/200/150
JTAG Port Timing Diagram
tTKC
tTKH
tTH
tTS
tTH
tTS
tTKQ
tTH
tTS
tTKL
JTAG Port AC Electrical Characteristics
Parameter
Symbol Min Max Unit
TCK Cycle Time
tTKC
50
—
ns
TCK Low to TDO Valid
tTKQ
—
20
ns
TCK High Pulse Width
tTKH
20
—
ns
TCK Low Pulse Width
tTKL
20
—
ns
TDI & TMS Set Up Time
tTS
10
—
ns
TDI & TMS Hold Time
tTH
10
—
ns
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: [e-mail].
Rev: 1.01 2/2005
26/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology