GS8161E18BT-V Datasheet, PDF(4/35 Page) GSI Technology – 1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs

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GS8161E18BT-V Datasheet, PDF (4/35 Pages) GSI Technology – 1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs

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TQFP Pin Description

Symbol

A0, A1

A

DQA

DQB

DQC

DQD

NC

BW

BA, BB, BC, BD

CK

GW

E1

G

ADV

ADSP, ADSC

ZZ

TMS

TDI

TDO

TCK

FT

LBO

TMS

TDI

TDO

TCK

VDD

VSS

VDDQ

Type

I

I

I/O

â

I

I

I

I

I

I

I

I

I

I

I

O

I

I

I

I

I

O

I

I

I

I

Preliminary

GS8161ExxB(T/D)-xxxV

Description

Address field LSBs and Address Counter preset Inputs

Address Inputs

Data Input and Output pins

No Connect

Byte WriteâWrites all enabled bytes; active low

Byte Write Enable for DQA, DQB Data I/Os; active low

Clock Input Signal; active high

Global Write EnableâWrites all bytes; active low

Chip Enable; active low

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

Core power supply

I/O and Core Ground

Output driver power supply

Rev: 1.01a 6/2006

4/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Â© 2004, GSI Technology

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