GS81302D18AGD-400I Datasheet, PDF (4/28 Pages) GSI Technology – 144Mb SigmaQuadTM-II Burst of 4 SRAM

Preliminary
GS81302D18/36AGD-400/375/333/300/250
Pin Description Table
Symbol
Description
Type
Comments
SA
Synchronous Address Inputs
Input
—
R
Synchronous Read
Input
Active Low
W
Synchronous Write
Input
Active Low
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x9/x18/x36 only
NW0–NW1
Nybble Write Control Pin
Input
Active Low
x8 only
K
Input Clock
Input
Active High
K
Input Clock
Input
Active Low
C
Output Clock
Input
Active High
C
Output Clock
Input
Active Low
TMS
Test Mode Select
Input
—
TDI
Test Data Input
Input
—
TCK
Test Clock Input
Input
—
TDO
Test Data Output
Output
—
V_REF
HSTL Input Reference Voltage
Input
—
ZQ
Output Impedance Matching Input
Input
—
Qn
Synchronous Data Outputs
Output
—
Dn
Synchronous Data Inputs
Input
—
D_off
Disable PLL when low
Input
Active Low
CQ
Output Echo Clock
Output
—
CQ
Output Echo Clock
Output
—
V_DD
Power Supply
Supply
1.8 V Nominal
V_DDQ
Isolated Output Buffer Supply
Supply
1.5 or 1.8 V Nominal
V_SS
Power Supply: Ground
Supply
—
NC
No Connect
—
—
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to V_DDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. C, C, K, K cannot be set to V_REF voltage.
Rev: 1.00a 5/2017
4/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2017, GSI Technology