GS81280Z18GT-250I Datasheet, PDF (4/23 Pages) GSI Technology – 144Mb Pipelined and Flow Through Synchronous NBT SRAM

GS81280Z18/36GT-400/333/250/200
TQFP Pin Descriptions
Symbol
A0, A1
A
CK
BA
BB
BC
BD
W
E1
E2
E3
G
ADV
CKE
DQA
DQB
DQC
DQD
ZZ
FT
LBO
V_DD
V_SS
V_DDQ
NC
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
In
I/O
I/O
I/O
I/O
In
In
In
In
In
In
—
NU
—
Description
Burst Address Inputs; Preload the burst counter
Address Inputs
Clock Input Signal
Byte Write signal for data inputs DQA1-DQA9; active low
Byte Write signal for data inputs DQB1-DQB9; active low
Byte Write signal for data inputs DQC1-DQC9; active low
Byte Write signal for data inputs DQD1-DQD9; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; Active High. For self decoded depth expansion
Chip Enable; Active Low. For self decoded depth expansion
Output Enable; active low
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
Core power supply
Ground
Output driver power supply
No Connect
Not Used—There is an internal chip connection to these pins, but they are unused by the device. They may
be left unconnected, tied Low (to V_SS), or tied High (to V_DDQ or V_DD).
Rev: 1.01 5/2017
4/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology