GS8161Z18BT-V Datasheet, PDF (23/35 Pages) GSI Technology – 18Mb Pipelined and Flow Through Synchronous NBT SRAM

Flow Through Mode Timing (NBT)
Preliminary
GS8161ZxxB(T/D)-xxxV
CK
CKE
E*
ADV
W
Bn
A0–An
DQ
G
Write A
Write B
Write B+1 Read C
tKL
tKH
tKC
Cont
Read D
Write E
Read F
Write G
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
A
B
tH
tS
D(A)
D(B)
C
tKQ
tLZ
D(B+1)
Q(C)
D
E
F
G
tKQX tKQ
tHZ
tLZ
tKQX
Q(D)
D(E)
Q(F)
D(G)
tOLZ
tOE
tOHZ
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V_DD. The JTAG output
drivers are powered by V_DDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V_DD or V_SS. TDO should be left unconnected.
Rev: 1.01a 6/2006
23/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology