GS8161Z18BT-V Datasheet, PDF (15/35 Pages) GSI Technology – 18Mb Pipelined and Flow Through Synchronous NBT SRAM

Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Note:
The burst counter wraps to initial state on the 5th clock.
Preliminary
GS8161ZxxB(T/D)-xxxV
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.01a 6/2006
15/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology