GS81302QT19E-250I Datasheet, PDF (23/28 Pages) GSI Technology – JEDEC-standard pinout and package

GS81302QT07/10/19/37E-318/300/250/200
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
Test Port Input Low Voltage
V_ILJ
–0.3
0.3 * V_DD
V
1
Test Port Input High Voltage
V_IHJ
0.7 * V_DD
V_DD +0.3
V
1
TMS, TCK and TDI Input Leakage Current
I_INHJ
–300
1
uA
2
TMS, TCK and TDI Input Leakage Current
I_INLJ
–1
100
uA
3
TDO Output Leakage Current
I_OLJ
–1
1
uA
4
Test Port Output High Voltage
V_OHJ
V_DD – 0.2
—
V
5, 6
Test Port Output Low Voltage
V_OLJ
—
0.2
V
5, 7
Test Port Output CMOS High
V_OHJC
V_DD – 0.1
—
V
5, 8
Test Port Output CMOS Low
V_OLJC
—
0.1
V
5, 9
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < V_DDn +1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.
2. V_ILJ  V_IN V_DDn
3. 0 V V_IN V_ILJn
4. Output Disable, V_OUT = 0 to V_DDn
5. The TDO output driver is served by the V_DD supply.
6. I_OHJ = –2 mA
7. I_OLJ = + 2 mA
8. I_OHJC = –100 uA
9. I_OLJC = +100 uA
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
V_DD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V_DD/2
Output reference level
V_DD/2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Load
TDO
50
30pF^*
V_DD/2
* Distributed Test Jig Capacitance
Rev: 1.00e 8/2017
23/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology