GS81314LD19GK-800 Datasheet, PDF (20/39 Pages) GSI Technology – Burst of 4 Single-Bank ECCRAM

GS81314LD19/37GK-933/800
State Truth Table
RST MRW LBKE R W SA D
1
X
X
X
X
X
X
0
1
X
0
X
V
X
0
0
1
X
X
X
X
0
1
X
1
See Clock Truth Table
0
0
0
X
Note: 1 = High; 0 = Low; V = Valid; X = don’t care.
SRAM State
Reset
Register Write Mode
Loopback Mode
Memory Mode
(Read, Write, NOP)
Q
NOP State
Undefined
Loopback
See Clock Truth
Table
Clock Truth Table
SA MRW R
W
Previous
Operation
Current
Operation
D
Q
CK CK CK CK
(t_n) (t_n) (t_n) (t_n)
(t_n–1)
(t_n)
KD KD KD KD CQ CQ CQ CQ
(t_n-1) (t_n-½)
(t_n)
(t_n+½) (t_n+5) (t_n+5½) (t_n+6) (t_n+6½)
X011
NOP
NOP
X
X
—
0
—
X01X
Write
NOP
D3
D4
—
0
—
X0X1
Read
NOP
X
X
—
Q3
Q4
—
V010
NOP
Write
D1
D2
D3
D4
0
—
V0X0
Read
Write
D1
D2
D3
D4
Q3
Q4
—
V00X
NOP
Read
X
X
—
Q1
Q2
Q3
Q4
V00X
Write
Read
D3
D4
—
Q1
Q2
Q3
Q4
V10X
NOP
Register Write
X
X
—
Undefined
Undefined
11X
NOP
NOP
X
X
—
0
—
Notes:
1. 1 = High; 0 = Low; V = Valid; X = don’t care.
2. D1, D2, D3, and D4 indicate the first, second, third, and fourth pieces of write data transferred during Write operations.
3. Q1, Q2, Q3, and Q4 indicate the first, second, third, and fourth pieces of read data transferred during Read operations.
4. Q pins are driven Low for one cycle in response to NOP and Write commands, 5 cycles after the command is sampled, except when pre-
ceded by a Read command.
Rev: 1.02 3/2016
20/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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