GS820H32AT Datasheet, PDF (19/23 Pages) GSI Technology – 64K x 32 2M Synchronous Burst SRAM

Sleep Mode Timing Diagram
GS820H32AT/Q-150/138/133/117/100/66
CK
ADSP
ADSC
ZZ
tS tH
tKC _{tKH tKL}
tZZS
tZZH
Snooze
tZZR
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in
a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in
transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to
manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised
to avoid excessive bus contention.
Rev: 1.04 3/2000
19/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
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