GS820H32AT Datasheet, PDF (11/23 Pages) GSI Technology – 64K x 32 2M Synchronous Burst SRAM

GS820H32AT/Q-150/138/133/117/100/66
AC Test Conditions
Parameter
Conditions
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
Output load
2.3V
0.2V
1V/ns
1.25V
1.25V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for t_LZ, t_HZ, t_OLZ and t_OHZ.
4. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
Output Load 2
2.5V
50Ω
30pF^*
DQ
225Ω
VT=1.25V
* Distributed Test Jig Capacitance
5pF^{* 225Ω}
DC Electrical Characteristics
Parameter
Input Leakage Current
(except mode pins)
ZZ Input Current
Mode Pin Input Current
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
Symbol Test Conditions
I_IL
V_IN = 0 to V_DD
I_INZZ
V_DD ≥ V_IN ≥ V_IH
0V ≤ V_IN ≤ V_IH
I_INM
V_DD ≥ V_IN ≥ V_IL
0V ≤ V_IN ≤ V_IL
I_OL
Output Disable,
V_OUT = 0 to V_DD
V_OH I_OH = - 8mA, V_DDQ=2.375V
V_OH I_OH = -8mA, V_DDQ=3.135V
V_OL
I_OL = 8mA
Min
-1uA
-1uA
-1uA
-300uA
-1uA
-1uA
1.7V
2.4V
Max
1uA
1uA
300uA
1uA
1uA
1uA
0.4V
Rev: 1.04 3/2000
11/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
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