GS8182Q09BD-200I Datasheet, PDF (19/36 Pages) GSI Technology – 18Mb SigmaQuad-IITM Burst of 2 SRAM

GS8182Q08/09/18/36BD-333/300/250/200/167/133
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter
Symbol
Min.
Output High Voltage
V_OH1
V_DDQ/2 – 0.12
Output Low Voltage
V_OL1
V_DDQ/2 – 0.12
Output High Voltage
V_OH2
V_DDQ – 0.2
Output Low Voltage
V_OL2
Vss
Notes:
1. I_OH = (V_DDQ/2) / (RQ/5) +/– 15% @ V_OH = V_DDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
2. I_OL = (V_DDQ/2) / (RQ/5) +/– 15% @ V_OL = V_DDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
3. Parameter tested with RQ = 250Ω and V_DDQ = 1.5 V or 1.8 V
4. 0Ω ≤ RQ ≤ ∞Ω
5. I_OH = –1.0 mA
6. I_OL = 1.0 mA
Max.
V_DDQ/2 + 0.12
V_DDQ/2 + 0.12
V_DDQ
0.2
Units
V
V
V
V
Notes
1, 3
2, 3
4, 5
4, 6
Operating Currents
-333
-300
-250
-200
-167
-133
Parameter
Symbol
Test Conditions
0 –40 0 –40 0 –40 0 –40 0 –40 0 –40 ^Notes
to to to to to to to to to to to to
70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C
Operating Current
(x36): DDR
I_DD
V_DD = Max, I_OUT = 0 mA _{1005 1015 935}
Cycle Time ≥ t_KHKH Min mA mA mA
945
mA
660 670 560 570 485
mA mA mA mA mA
495
mA
415
mA
425
mA
2, 3
Operating Current
(x18): DDR
I_DD
V_DD = Max, I_OUT = 0 mA
Cycle Time ≥ t_KHKH Min
860 870 800
mA mA mA
810
mA
595 605 500 510 435
mA mA mA mA mA
445
mA
375
mA
385
mA
2, 3
Operating Current (x9):
DDR
I_DD
V_DD = Max, I_OUT = 0 mA
Cycle Time ≥ t_KHKH Min
860 870 800
mA mA mA
810
mA
595 605 500 510 435
mA mA mA mA mA
445
mA
375
mA
385
mA
2, 3
Operating Current (x8):
DDR
I_DD
V_DD = Max, I_OUT = 0 mA
Cycle Time ≥ t_KHKH Min
860 870 800
mA mA mA
810
mA
595 605 500 510 435
mA mA mA mA mA
445
mA
375
mA
385
mA
2, 3
Standby Current
(NOP): DDR
Device deselected,
I_SB1
I_OUT = 0 mA, f = Max,
All Inputs ≤ 0.2 V or
215 225
mA mA
210
mA
220
mA
175 185 165 175
mA mA mA mA
155
mA
165
mA
150
mA
160
mA
2, 4
≥ V_DD – 0.2 V
Notes:
1. Power measured with output pins floating.
2. Minimum cycle, I_OUT = 0 mA
3. Operating current is calculated with 50% read cycles and 50% write cycles.
4. Standby Current is only after all pending read and write burst operations are completed.
Rev: 1.03d 11/2011
19/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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