GS8182Q09BD-200I Datasheet, PDF (14/36 Pages) GSI Technology – 18Mb SigmaQuad-IITM Burst of 2 SRAM

GS8182Q08/09/18/36BD-333/300/250/200/167/133
Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Read Truth Table
A
R
Output Next State
K↑
K↑
K↑
(t_n)
(t_n)
(t_n)
X
1
Deselect
V
0
Read
Notes:
1. X = Don’t Care, 1 = High, 0 = Low, V = Valid.
2. R is evaluated on the rising edge of K.
3. Q0 and Q1 are the first and second data output transfers in a read.
Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Write Truth Table
A
W
BWn
BWn
Input Next State
K↑
K↑
(t_{n + ½})
(t_n)
K↑
K↑
(t_n)
(t_{n + ½})
K ↑, K ↑
(t_n), (t_{n + ½})
V
0
0
0
Write Byte Dx0, Write Byte Dx1
V
0
0
1
Write Byte Dx0, Write Abort Byte Dx1
V
0
1
0
Write Abort Byte Dx0, Write Byte Dx1
X
0
1
1
Write Abort Byte Dx0, Write Abort Byte Dx1
X
1
X
X
Deselect
Notes:
1. X = Don’t Care, H = High, L = Low, V = Valid.
2. W is evaluated on the rising edge of K.
3. D0 and D1 are the first and second data input transfers in a write.
4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.).
Q
K↑
(t_n+1)
Hi-Z
Q0
D
K↑
(t_n)
D0
D0
X
X
X
Q
K↑
(t_n+1½)
Hi-Z
Q1
D
K↑
(t_{n + ½})
D1
X
D1
X
X
Rev: 1.03d 11/2011
14/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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