GS81314PQ36GK-120I Datasheet, PDF (19/39 Pages) GSI Technology – Burst of 2 Multi-Bank ECCRAM

GS81314PQ18/36GK-133/120/106
Address Bus Utilization and Bank Access Restrictions
The address bus is a non-multiplexed DDR bus. Up to two memory addresses may be loaded per cycle - a read address at CK and
/or a write address at CK; consequently two memory operations - a Read and a Write - may be initiated per clock cycle. The address
bus is also sampled at CK during a Register Write operation.
Address Bit Encoding
Command
Addr
Load
Device
21
20
19
18
17
16
15
14
SA Address Bits
13 12 11 10 9 8
7
6
x36 NU
Address
BA
Read
CK
x18
Address
BA
x36 NU
Address
BA
Write
CK
x18
Address
BA
Register
Write
CK
x36 NU X X X X X X X X X X
x18 X X X X X X X X X X X
Register Data
Register Data
Note: BA = Bank Address
543210
Address
BA
Address
BA
Address
BA
Address
BA
Register # X
Register # X
Bank Access Restrictions
1. In -133 devices only, Read in cycle “n” must be to a different bank than Read in cycle “n-1”.
2. In all devices, Read in cycle “n” must be to a different bank than Write in cycle “n-5” (due to Write Buffering).
Rev: 1.09 5/2016
19/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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