GS820H32T Datasheet, PDF (17/23 Pages) GSI Technology – 64K x 32 2M Synchronous Burst SRAM

Pipelined SCD Read Cycle Timing
GS820H32T/Q-150/138/133/117/100/66
CK
ADSP
ADSC
ADV
An
GW
BW
BWA - BWD
E1
E2
E3
G
DQA - DQD
Single Read
tS ^tH
Burst Read
tKH ^tKL
tKC _{ADSP is blocked by E1 inactive}
tS tH
ADSC initiated read
tS tH
Suspend Burst
tS tH
RD1
tS
RD2
RD3
tH
tS
tH
tS tH
tS tH
tS _tH
E1 masks ADSP
E2 and E3 only sampled with ADSP or ADSC
tOE
tOHZ
tOLZ
tKQX
Hi-Z
Q1A
Q2A Q2B
Q2C
tLZ
tKQ
Deselected with E2
tKQX
Q2D
Q3A
tHZ
Rev: 1.03 2/2000
17/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
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