GS82582D19GE-400I Datasheet, PDF (15/26 Pages) GSI Technology – JEDEC-standard pinout and package

GS82582D19/37GE-450/400/375/333
AC Electrical Characteristics (Continued)
Parameter
Symbol
-450
Min
Max
-400
Min
Max
-375
Min Max
-333
Min Max
Control Input Hold Time
(BWX)
t_KHIX
0.22
—
0.28
—
0.28
—
0.28
—
ns
3
Data Input Hold Time
t_KHDX
0.22
—
0.28
—
0.28
—
0.28
—
ns
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W.
3. Control singles are BW0, BW1 and (BW2, BW3 for x36).
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. V_DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V_DD and input clock are stable.
6. After device power-up, 20s of stable input clocks (as specified by t_KInit) must be supplied before reads and writes are issued.
Rev: 1.04 4/2016
15/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology