GS82582D19GE-400I Datasheet, PDF (14/26 Pages) GSI Technology – JEDEC-standard pinout and package

GS82582D19/37GE-450/400/375/333
AC Electrical Characteristics
Parameter
Symbol
-450
Min
Max
-400
Min
Max
-375
Min Max
-333
Min Max
Clock
K, K Clock Cycle Time
t_KHKH
2.2
8.4
2.5
8.4
2.66
8.4
3.0
8.4
ns
tK Variable
t_KVar
—
0.15
—
0.2
—
0.2
—
0.2
ns
4
K, K Clock High Pulse Width
t_KHKL
0.4
—
0.4
—
0.4
—
0.4
—
cycle
K, K Clock Low Pulse Width
t_KLKH
0.4
—
0.4
—
0.4
—
0.4
—
cycle
K to K High
t_KHKH
0.94
—
1.06
—
1.13
—
1.28
—
ns
K to K High
t_KHKH
0.94
—
1.06
—
1.13
—
1.28
—
ns
DLL Lock Time
t_KLock
2048
—
2048
—
2048
—
2048
—
cycle 5
K Static to DLL reset
t_KReset
30
—
30
—
30
—
30
—
ns
K, K Clock Initialization
Output Times
t_KInit
20
—
20
—
20
—
20
—
s
6
K, K Clock High to Data Output Valid
t_KHQV
—
0.45
—
0.45
—
0.45
—
0.45
ns
K, K Clock High to Data Output Hold
t_KHQX
–0.45
—
–0.45
—
–0.45 — –0.45 —
ns
K, K Clock High to Echo Clock Valid
t_KHCQV
—
0.37
—
0.45
—
0.45
—
0.45
ns
K, K Clock High to Echo Clock Hold
t_KHCQX
–0.37
—
–0.45
—
–0.45 — –0.45 —
ns
CQ, CQ High Output Valid
t_CQHQV
—
0.15
—
0.2
—
0.2
—
0.2
ns
CQ, CQ High Output Hold
t_CQHQX
–0.15
—
–0.2
—
–0.2
—
–0.2
—
ns
CQ, CQ High to QVLD
t_QVLD
–0.15
0.15
–0.2
0.2
–0.2
0.2
–0.2
0.2
ns
CQ Phase Distortion
t_CQHCQH
t_CQHCQH
0.85
—
1.0
—
1.08
—
1.25
—
ns
K Clock High to Data Output High-Z
t_KHQZ
—
0.45
—
0.45
—
0.45
—
0.45
ns
K Clock High to Data Output Low-Z
Setup Times
t_KHQX1
–0.45
—
–0.45
—
–0.45 — –0.45 —
ns
Address Input Setup Time
Control Input Setup Time
(R, W)
Control Input Setup Time
(BWX)
t_AVKH
0.275
—
0.4
—
0.4
—
0.4
—
ns
1
t_IVKH
0.275
—
0.4
—
0.4
—
0.4
—
ns
2
t_IVKH
0.22
—
0.28
—
0.28
—
0.28
—
ns
3
Data Input Setup Time
Hold Times
t_DVKH
0.22
—
0.28
—
0.28
—
0.28
—
ns
Address Input Hold Time
t_KHAX
0.275
—
0.4
—
0.4
—
0.4
—
ns
1
Control Input Hold Time
(R, W)
t_KHIX
0.275
—
0.4
—
0.4
—
0.4
—
ns
2
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W.
3. Control singles are BW0, BW1 and (BW2, BW3 for x36).
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. V_DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V_DD and input clock are stable.
6. After device power-up, 20s of stable input clocks (as specified by t_KInit) must be supplied before reads and writes are issued.
Rev: 1.04 4/2016
14/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology