GS81314LD37GK-800 Datasheet, PDF (13/39 Pages) GSI Technology – Burst of 4 Single-Bank ECCRAM

GS81314LD19/37GK-933/800
LBKE
0
1
0
Loopback Mode Enable
Disable Loopback Mode
Enable Loopback Mode
POR/RST Default
LBK[1:0]
00
01
10
11
00
Loopback Mode Select
XOR Loopback Mode, input group #1
XOR Loopback Mode, input group #2
INV Loopback Mode, input group #1
INV Loopback Mode, input group #2
POR/RST Default
Note: In the ODT Control register bit definitions below, MZT[1:0] and PZT[1:0] pins set the default state of the register bits at pow-
er-up and whenever RST is asserted High. The register bits can then be overwritten (via Register Write Mode), while RST is de-as-
serted Low, to change the state of the feature controlled by the register bits.
Input Clock ODT Control
CKZT1
CKZT0
KDZT1
KDZT0
0
0
0
1
1
0
1
1
00, if MZT[1:0] = 00 or PZT0 = 0
01, if MZT[1:0] = 01 and PZT0 = 1
10, if MZT[1:0] = 10 and PZT0 = 1
11, if MZT[1:0] = 11 and PZT0 = 1
disabled
enabled: PU = PD = RT
enabled: PU = PD = 2*RT
reserved
POR/RST Default
Address & Control ODT Control
AZT1
AZT0
CZT1
CZT0
0
0
0
1
1
0
1
1
00, if MZT[1:0] = 00 or PZT1 = 0
01, if MZT[1:0] = 01 and PZT1 = 1
10, if MZT[1:0] = 10 and PZT1 = 1
11, if MZT[1:0] = 11 and PZT1 = 1
disabled
enabled: PU = PD = RT
enabled: PU = PD = 2*RT
reserved
POR/RST Default
Write Data ODT Control
DZT1
DZT0
0
0
0
1
1
0
1
1
00, if MZT[1:0] = 00
01, if MZT[1:0] = 01
10, if MZT[1:0] = 10
11, if MZT[1:0] = 11
disabled
enabled: PU = PD = RT
enabled: PU = PD = 2*RT
reserved
POR/RST Default
Rev: 1.02 3/2016
13/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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