GS81332QT19CE-350M Datasheet, PDF (12/30 Pages) GSI Technology – Rad-Hard SRAM 288Mb/144Mb/72Mb Burst of 2 SigmaQuad-II+TM

Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Read Truth Table
A
R
Output Next State
K
K
K
(t_n)
(t_n)
(t_n)
X
1
Deselect
V
0
Read
Notes:
1. X = Don’t Care, 1 = High, 0 = Low, V = Valid.
2. R is evaluated on the rising edge of K.
3. Q0 and Q1 are the first and second data output transfers in a read.
Preliminary
GS82612QT19/37CE-350M/250M
GS81332QT19/37CE-350M/250M
GS8692QT19/37CE-350M/250M
Q
K
(t_n+2)
Hi-Z
Q0
Q
K
(t_n+2½)
Hi-Z
Q1
Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Write Truth Table
A
W
BWn
BWn
Input Next State
D
K
K
K
K
K K 
K
(t_{n + ½})
(t_n)
(t_n)
(t_{n + ½})
(t_n), (t_{n + ½})
(t_n)
V
0
0
0
Write Byte Dx0, Write Byte Dx1
D0
V
0
0
1
Write Byte Dx0, Write Abort Byte Dx1
D0
V
0
1
0
Write Abort Byte Dx0, Write Byte Dx1
X
X
0
1
1
Write Abort Byte Dx0, Write Abort Byte Dx1
X
X
1
X
X
Deselect
X
Notes:
1. X = Don’t Care, H = High, L = Low, V = Valid.
2. W is evaluated on the rising edge of K.
3. D0 and D1 are the first and second data input transfers in a write.
4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.).
D
K
(t_{n + ½})
D1
X
D1
X
X
Rev: 1.01 7/2017
12/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2017, GSI Technology