GS8180QV18BGD-200 Datasheet, PDF (11/28 Pages) GSI Technology – 18Mb Burst of 2 SigmaQuad SRAM

GS8180QV18/36BD-200/167
Separate I/O Burst of 2 SigmaQuad SRAM Read Truth Table
A
R
Output Next State
K↑
K↑
K↑
(t_n)
(t_n)
(t_n)
X
1
Deselect
V
0
Read
Notes:
1. X = Don’t Care, 1 = High, 0 = Low, V = Valid.
2. R is evaluated on the rising edge of K.
3. Q0 and Q1 are the first and second data output transfers in a read.
Separate I/O Burst of 2 SigmaQuad SRAM Write Truth Table
A
W
BWn
BWn
Input Next State
K↑
K↑
(t_{n + ½})
(t_n)
K↑
K↑
(t_n)
(t_{n + ½})
K ↑, K ↑
(tn), (tn + ½)
V
0
0
0
Write Byte Dx0, Write Byte Dx1
V
0
0
1
Write Byte Dx0, Write Abort Byte Dx1
V
0
1
0
Write Abort Byte Dx0, Write Byte Dx1
X
0
1
1
Write Abort Byte Dx0, Write Abort Byte Dx1
X
1
X
X
Deselect
Notes:
1. X = Don’t Care, H = High, L = Low, V = Valid.
2. W is evaluated on the rising edge of K.
3. D0 and D1 are the first and second data input transfers in a write.
4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.).
x18 Byte Write Enable (BWn) Truth Table
BW0
BW1
1
1
0
1
1
0
0
0
D0–D8
Don’t Care
Data In
Don’t Care
Data In
Q
K↑
(t_n+1)
Hi-Z
Q0
Q
K↑
(t_n+1½)
Hi-Z
Q1
D
D
K↑
K↑
(t_n)
(t_{n + ½})
D0
D1
D0
X
X
D1
X
X
X
X
D9–D17
Don’t Care
Don’t Care
Data In
Data In
Rev: 1.02b 11/2011
11/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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