GS8673EQ18BGK-625I Datasheet, PDF (10/31 Pages) GSI Technology – On-Chip ECC with virtually zero SER

GS8673EQ18/36BK-675/625/550/500
Low Power NOP Mode
When input termination is enabled on the Address (SA) and Write Data (D) inputs, those inputs can be placed in Low Power NOP
(LP NOP) mode via the synchronous ADZT1 input. When NOP operations are initiated with ADZT1 High, the termination
pull-ups on the SA and D inputs are disabled, thereby reducing the DC power associated with those inputs.
LP NOP Truth Table
R
W
ADZT1
Current Operation
SA, D Pull-Up
↑CK
↑CK
↑CK
(t_n)
(t_n)
(t_n)
(t_n)
↑CK
(t_n+2)
X
X
0
Any
Enabled
X
X
1
Any
Notes:
1. 1 = input High; 0 = input Low; X = input don’t care.
2. ADZT1 should only be driven High during NOP operations; SA, D input timing is not guaranteed in LP NOP Mode.
3. SA, D should be driven Low (or tri-stated) during LP NOP Mode, to take advantage of the power-saving feature.
Disabled
LP NOP Timing Specifications
Parameter
Symbol
Min
CK Clock High to SA Pull-up Enable / Disable
t_KHAZTV
0
CK Clock High to D Pull-Up Enable / Disable
t_KHDZTV
–0.4
Max
Units
2.0
ns
0.4
ns
Rev: 1.06 5/2012
10/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology