GS81302TT06 Datasheet, PDF (10/29 Pages) GSI Technology – 144Mb SigmaDDRTM-II+ Burst of 2 SRAM

GS81302TT06/11/20/38E-500/450/400/350
Burst of 2 Nybble Write Clock Truth Table
NW
NW
Current Operation
D
D
K↑
(t_{n + 1})
T
K↑
(t_{n + 1½})
T
K↑
(t_n)
Write
Dx stored if NWn = 0 in both data transfers
K↑
(t_{n + 1})
D1
K↑
(t_{n + 1½})
D2
T
F
F
T
Write
Dx stored if NWn = 0 in 1st data transfer only
Write
Dx stored if NWn = 0 in 2nd data transfer only
D1
X
X
D2
F
F
Write Abort
No Dx stored in either data transfer
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
X
X
x36 Byte Write Enable (BWn) Truth Table
BW0 BW1 BW2 BW3
1
1
1
1
0
1
1
1
1
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
D0–D8
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
D18–D26
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
D27–D35
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Data In
Data In
Data In
Data In
Rev: 1.00b 11/2011
10/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology