GS881Z18T Datasheet, PDF (1/34 Pages) GSI Technology – 8Mb Pipelined and Flow Through Synchronous NBT SRAMs

Preliminary
GS881Z18/36T-11/100/80/66
100-Pin TQFP _{8Mb Pipelined and Flow Through} 100 MHz–66 MHz
Commercial Temp
Industrial Temp
Synchronous NBT SRAMs
3.3 V V_DD
2.5 V and 3.3 V V_DDQ
Features
• 512K x 18 and 256K x 36 configurations
• User-configurable Pipelined and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
• Read-Write-Read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• Pin-compatible with 2M, 4M and 16M devices
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered, address, data, and control
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
Pipeline
3-1-1-1
Flow Through
2-1-1-1
-11 -100 -80
-66
t_{Cycle 10 ns 10 ns 12.5 ns 15 ns}
t_KQ 4.5 ns 4.5 ns 4.8 ns 5 ns
I_DD 210 mA 210 mA 190 mA 170 mA
t_KQ
11 ns 12 ns 14 ns 18 ns
t_Cycle 15 ns 15 ns 15 ns 20 ns
I_DD 150 mA 150 mA 130 mA 130 mA
Functional Description
The GS881Z18/36T is an 8Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS881Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising-edge-triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge-triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS881Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
A
B
C
D
E
F
Read/Write
R
W
R
W
R
W
Flow Through
Data I/O
Pipelined
Data I/O
Q_A
D_B
Q_C
D_D
Q_E
Q_A
D_B
Q_C
D_D
Q_E
Rev: 1.10 8/2000
1/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.